Full-custom design

By contrast, Full-Custom ASIC Design defines all the photo lithographic layers of the device. Full Custom Design is used for both ASIC design and for Standard Product design.

The benefits of Full-Custom Design usually include :

Reduced area (and therefore recurring component cost), performance improvements and also the ability to integrate (include) analog components and other pre-designed (and thus fully verified) components such as microprocessor cores that form a System-On-Chip.

The disadvanstages of Full-Custom can include :

Increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the Computer Aided Design (CAD) system and a much higher skill requirement on the part of the design team.

Gate array design

Gate Array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected. The physical design process then defines the interconnections of the final device. For most ASIC manufacturers, this consists of from two to as many as five metal layers, each metal layer running perpendicular to the one below it. Non-recurring engineering costs are much lower as photo-lithographic masks are required only for the metal layers, and production cycles are much shorter as metallization is a comparatively quick process.

Gate Array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the interconnect.
Pure, logic only Gate Array Design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices, such as FPGAs (Field Programmable Gate Arrays), which can be programmed by the user and thus offer minimal tooling charges (Non-recurring engineering (NRE)), marginally increased piece part cost and comparable performance. Today Gate Arrays are evolving into Structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic. This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and "system on a chip" requires far more than just logic blocks.
The term "Gate Array" is almost synonymous and interchangeable with the term "Semi-Custom". Which term you would use depends on who you are; if you are a process engineer, more likely than not you would use "Semi-Custom" whereas if you are a logic (or gate level) designer, "Gate-Array" would probably be your term of choice.

Standard Cell Design

In the mid 1980s, most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, which could also be represented in third party tools. Standard Cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.

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